1. Field of the Invention
The present invention relates to semiconductor integrated circuits, and, more particularly, the present invention relates to a semiconductor integrated circuit with preferably fast operation and power-saving properties, as well as methods and programs for designing the semiconductor integrated circuit.
2. Description of the Background
Insulated gate field effect transistors (referred to as “MOS” or “MOSFET” herein) have preferably high integration and power saving characteristics. These beneficial characteristics account for the transistors wide use in various semiconductor integrated circuit devices. The on/off (switching) characteristics of the MOS are determined by the threshold voltage. To improve the MOS's driving ability, as well as to improve the operational speed of the subject circuit, it is effective to set a lower threshold voltage for the MOS. It should be noted have that an enhancement type MOS takes a positive value while the PMOS takes a negative value as the threshold voltage. Hereinafter, unless otherwise specifically mentioned, the threshold voltage level refers to an absolute value.
On the other hand, in the case where an excessively low threshold voltage is set for the MOS, the MOS cannot be turned off completely even when the gate-source voltage thereof is set to 0. The subthreshold leakage current therefore increases. For an LSI (Large Scale Integration) that is required to have the properties of high integration and low power consumption, the power consumption caused by such a leakage current in the stand-by state increases to a point where it is no longer negligible.
To address these complications, the official gazette of JP-A 195976/1999 discloses a technique that configures an LSI using a plurality of MOSs that have different threshold voltages. According to the described technique, priority is given to lower threshold voltage MOSs used for gate cells located in a path which requires faster operational speed and higher threshold voltage MOSs are used for other gate cells so that the LSI can cope with both fast operation and low power consumption properties.
An LSI, in which a plurality of MOSs with different threshold voltages are mixed in this way may be designed as follows. Initially, logical synthesis is undertaken with gate cells comprised of high threshold voltage MOSs, and the delay of each path in the logical-synthesized circuit block is then evaluated. Thereafter, each gate cell in a path that has a significant delay and determines the operation frequency of the subject circuit (e.g., the “critical path”) is replaced with a gate cell comprised of low threshold voltage MOSs.
In the case of the above conventional technique, because a gate cell composed of high threshold voltage MOSs is used for the first logical synthesis step, the first step cannot satisfy a fast operational speed requirement of the circuit when such a speed requirement is high. It is therefore expected that the logical synthesis step may often be repeated many times. In spite of this, it may be possible to reduce the logical synthesizing time if a fast operation circuit is obtained while the low power consumption property is kept up to a certain degree in the first logical synthesis step.
Multiple-input logic gates (especially, logic gates with four or more inputs) are not typically used in conventional logical synthesis. In the case of a 4-input NAND gate, for example, because four NMOSs are connected serially, the subject circuit becomes slow in operation speed when high threshold voltage MOSs are used for the gate. This occurs because the operational current is insufficient. This is the reason that it is rare to find a logical circuit comprised of multiple-input logic gates.
Under these circumstances, the present invention preferably provides a semiconductor integrated circuit that is well-balanced between low power consumption and fast operational properties. The present invention also provides a method for enabling logical synthesis so as to design such a semiconductor integrated circuit in a reduced amount of time.